1. Field
The present disclosure relates generally to reference clocks in integrated circuits. More specifically the present disclosure relates to maintaining constant duty cycle in a reference clock over multiple power operating modes.
2. Background
In a typical power management integrated circuit (PMIC) system, there are usually a few reference clock outputs distributed to external RF chips (such as WAN, WLAN, GPS, etc.) used in portable devices. To meet tight phase noise requirements for RF clock delivery, an on-chip crystal oscillator (XO) is usually designed to provide an accurate clock source with its frequency set by an external crystal (XTAL).
In wireless communication systems there is a need for a reference clock to synchronize signals. A wireless communication system may support communication for multiple wireless communication devices at the same time. In use, a wireless communication device may communicate with one or more base stations by transmissions on the uplink and downlink. Base stations may be referred to as access points, Node Bs, or other similar terms. The uplink or reverse link refers to the communication link from the wireless communication device to the base station, while the downlink or forward link refers to the communication from the base station to the wireless communication devices.
Wireless communication systems may be multiple access systems capable of supporting communication with multiple users by sharing the available system resources, such as bandwidth and transmit power. Examples of such multiple access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, wideband code division multiple access (WCDMA) systems, global system for mobile (GSM) communication systems, enhanced data rates for GSM evolution (EDGE) systems, and orthogonal frequency division multiple access (OFDMA) systems.
Referring to FIG. 1, a typical reference clock output signal 130 with multiple power modes is delivered from the XO 105 in the power management integrated circuit (PMIC) 100 to a radio frequency (RF) section 110 including a radio frequency (RF) doubler 115 and a phase lock loop (PLL) 120. In order to convert the sinusoidal oscillation signal to a rail-to-rail signal (square wave) to be used with the RF devices, one or more programmable power buffers 125 needs to be inserted after the XO 105 before delivering the reference clock. The power programmable buffer chain 125 of amplification in the PMIC 100 sets the power mode level of the output reference clock signal 130. A higher power mode (compared with a normal power mode) is usually needed when lower phase noise at the clock output 130 is needed for better RF quality. The normal power mode is used to save power and improve battery life when the phase noise requirement is less stringent.
The RF device usually needs a good duty cycle from the reference clock under both normal power mode (NPM) and high power mode (HPM). For example, a Long Term Evolution (LTE) chip may typically need a duty cycle in the range ˜48%-52%, which is preferably kept stable (within ±0.1%) over multiple clock power modes. If the duty cycle of the output reference clock 130 is degraded in high power mode (HPM) relative to NPM, it can cause unwanted PLL reference and fractional spurs on the RF chip.
Thus there is a need to design a multi-power mode reference clock with constant and good duty cycle over multiple power modes.